1. Field of the Invention
The present invention relates to a driving circuit of a liquid crystal display device, and particularly to a driving circuit for driving signal lines.
2. Description of the Related Art
As a liquid crystal display device having a built-in driving circuit for signal lines and scan lines, there is known a device manufactured by using thin film transistors made of polysilicon.
FIG. 2 is a schematic view showing a conventional liquid crystal display device having a built-in driving circuit.
In FIG. 2, signal lines 206, 207 and 208 are arranged in the row direction, scanning lines 203, 204 and 205 are arranged in the column direction, and pixel transistors 224 and 225 are arranged in matrix at intersection points of those lines. A gate terminal of the thin film transistor 224 is connected to the scanning line 203, a source terminal thereof is connected to the signal line 206, and a drain terminal thereof is connected to a pixel electrode 226.
Each of the signal lines is designed to input a video signal inputted from a video input terminal to the source terminal of the pixel transistor, and is driven by a signal line driving circuit 201. Each of the scan lines is designed to input a scanning signal to the gate terminal of the pixel transistor and is driven by a scan line driving circuit 202.
The signal line driving circuit 201 is constituted by a shift register 216 and analog switches 218, 219 and 220. This system is called dot-sequential driving, and is common in a liquid crystal display device having a built-in driving circuit.
The shift register includes an input terminal 215 for inputting a start pulse, clock input terminals 208 and 209 for sequentially shifting a pulse, and power supply terminals 213 and 214. The outputs 221, 222 and 223 of the shift register are connected to the analog switches 218, 219 and 220.
FIG. 3 shows operation waveforms of the shift register.
When clock pulses CL1 and CL1b are inputted, a start pulse is shifted according to rising and falling of the clock.
As a result, an analog switch selection pulse is outputted to the respective outputs of the shift register.
This output is inputted to the analog switches 218, 219 and 220, and the respective analog switches are turned on only during the period of the pulse. When the analog switch is turned on, the video line 210, 211, or 212 and the signal line 206, 207 or 208 at both ends of the analog switch are short-circuited during the period, and data of the video line are written into the signal line. The data written into the signal line are inputted into pixel transistor connected to the selected scan line and are written into the pixel electrode.
The transmittance of a liquid crystal is changed by voltage between the pixel electrode and the opposite substrate so that gradation display is made.
FIGS. 4 and 5 show manufacturing steps of a conventional liquid crystal display device.
Manufacturing steps of obtaining a conventional monolithic type active matrix circuit will be described below with reference to FIGS. 4 and 5. The steps relate to a low temperature polysilicon process. The left sides of FIGS. 4 and 5 show manufacturing steps of a TFT of a driving circuit and the right sides thereof show manufacturing steps of a TFT of an active matrix circuit, respectively.
First, a silicon oxide film with a thickness of 1000 to 3000 Å is formed as an underlayer oxide film 402 on a glass substrate 401. As a method of forming the silicon oxide film, it is appropriate to use a sputtering method or a plasma CVD method in an oxygen atmosphere.
Then an amorphous silicon film with a thickness of 300 to 1500 Å, preferably 500 to 1000 Å is formed by a plasma CVD method or an LPCVD method. Then heat annealing is carried out at a temperature of 500° C. or more, preferably 500 to 600° C. to crystallize the silicon film or to raise crystallinity thereof. The crystallinity may further be raised by light (laser or the like) annealing after the crystallization by the heat annealing.
Moreover, at the crystallization by the heat annealing, an element (catalytic element) for promoting crystallization of silicon may be added as disclosed in Japanese Patent Unexamined Publication No. Hei. 6-244103 and No. Hei. 6-244104.
Next, the silicon film is etched to form an active layer 403 (for a P-channel TFT) and an active layer 404 (for an N-channel TFT) of the island-like driving circuit, and an active layer 405 of a TFT (pixel TFT) of the matrix circuit. Further, a gate insulating film of silicon oxide with a thickness of 500 to 2000 Å is formed by a sputtering method in an oxygen atmosphere. A plasma CVD method may be used for the method of forming the gate insulating film. In the case where the silicon oxide film is formed by the plasma CVD method, it was preferable to use nitrous oxide (N2O) or oxygen (O2) and monosilane (SiH4) as a raw material gas.
Thereafter, aluminum with a thickness of 2000 to 6000 Å is formed on the entire surface of the substrate by a sputtering method. Here, aluminum may contain silicon, scandium, palladium, or the like so as to prevent hillocks from occurring by a subsequent thermal process. This is etched to form gate electrodes 407, 408 and 409 (FIG. 4A).
Next, this aluminum is subjected to anodic oxidation. The surfaces of the aluminum become aluminum oxides 410, 411, and 412 by the anodic oxidation so that they come to have effects as insulators (FIG. 4B).
Next, a mask 413 of photoresist covering the active layer of the P-channel TFT is formed. Then phosphorus is implanted by an ion doping method with phosphine as a doping gas. The dosage is made 1×1012 to 5×1013 atoms/cm2. As a result, high N-type regions (source, drain) 414 and 415 are formed (FIG. 4C).
Next, a mask 416 of photoresist covering the active layer of the N-channel TFT and the active layer of the pixel TFT is formed. Then boron is implanted again by an ion doping method with diborane (B2H6) as a doping gas. The dosage is made 5×1014 to 8×1015 atoms/cm2. As a result, P-type regions 417 are formed. By the above doping steps, the high N-type regions (source, drain) 414 and 415, and the high P-type regions (source, drain) 417 are formed (FIG. 4D).
Thereafter, heat annealing at 450 to 850° C. for 0.5 to 3 hours is carried out to repair damages produced by doping and to activate doping impurities so that crystallinity of silicon is recovered. Then a silicon oxide film with a thickness of 3000 to 6000 Å is formed as an interlayer insulating film 418 on the entire surface by a plasma CVD method. This film may be a silicon nitride film or a multilayer film of a silicon oxide film and a silicon nitride film. Then the interlayer insulating film 418 is etched by a wet etching method or a dry etching method to form contact holes to the source/drain.
Then an aluminum film or a multilayer film of titanium and aluminum with a thickness of 2000 to 6000 Å is formed by a sputtering method. This film is etched to form electrode/wiring lines 419, 420, and 421 of the peripheral circuit and electrode/wiring lines 422 and 423 of the pixel TFT (FIG. 5E).
Further, polyimide with a thickness of 10000 Å is applied to form a second interlayer film 424. Next, titanium with a thickness of 2000 to 3000 Å is formed and is etched to form a black matrix 426 on the TFT. Further, polyimide with a thickness of 5000 to 6000 Å is applied to form a third interlayer film. Next, the second and third interlayer films are etched to form a contact hole reaching the electrode 423 of the TFT. Finally, an ITO (indium-tin oxide) film formed by a sputtering method and having a thickness of 500 to 1500 Å is etched to form a pixel electrode 425. In this way, the peripheral driving circuit and the active matrix circuit are integrally formed (FIG. 5F).
FIG. 6 shows a pattern of a conventional shift register. Numerals 501 to 506 indicate clock lines and numerals 507 and 508 indicate power supply terminals, respectively.
In a driving circuit of a conventional liquid crystal display device, in the case where clock wiring lines, video signal wiring lines, and control wiring lines of a shift register are formed, those wiring lines are formed at the same time as source and drain electrodes of a thin film transistor. The source/drain electrodes are used because the sheet resistance thereof is normally lower than a gate electrode material. In general, aluminum is used for the source/drain electrodes and the sheet resistance thereof is 0.1 Ω to 0.2 Ω.
As parasitic capacitance added to those wiring lines, inter-wiring capacitance between other wiring lines, and cross capacitance are conceivable. The inter-wiring capacitance has relation shown in FIG. 7, and as an interval between wiring lines becomes wide, the capacitance becomes small.
In the case where it is desired to raise frequencies of signals to be transmitted through the clock lines, video lines, control signal lines and the like, the foregoing wiring resistance and parasitic capacitance lower the frequency characteristics, which becomes a problem.
Here, it is assumed that the shift register shown in FIG. 6 has 300 stages, one stage being 250 μm. The explanation will be hereinafter made under this condition.
In the forgoing case where a wiring line and other wiring line cross each other, it is general to make crossing with gate electrode wiring lines. In this case, first interlayer film capacitance becomes parasitic capacitance.
When the interlayer film is formed of an oxide film with a thickness of 5000 Å and the width of a cross wiring line is 5 μm, the parasitic capacitance is 0.069 fF/μm2*5 μm*30 μm=10.3 fF. When there are 1.66 cross points for the foregoing wiring line of 250 μm, parasitic capacitance of 10.3 fF*1.66=17.1 fF is generated. Besides, when the interval of wiring lines is 5 μm, the inter-wiring capacitance becomes 0.063 fF/μm*250 μm*2=31.5 fF per 250 μm. In total, capacitance becomes 48.6 fF.
FIG. 9 shows the result of simulation for a delay amount under the assumption that the shift register is equivalent to a 300-stage resistor/capacitor ladder circuit shown in FIG. 8. The delay time is 2.8 ns, and in the case where the frequency is ten and several MHz, the rate of delay is 5%.
The same is true for a video signal line subjected to sampling by an analog switch. FIG. 10 is a plan view showing a conventional analog switch. Numerals 901 to 903 are denoted as video signal lines, numerals 904 to 909 are denoted as outputs of the shift register, numerals 910 to 912 are denoted as signal lines, and numerals 913 to 918 are denoted as analog switch transistor, respectively.
It is assumed that RGB three colors are made one, a pitch is 300 μm, and the number of stages is 300. When the wiring width is 30 μm, 300 μm, the wiring resistance becomes 2 Ω.
Similarly to the shift register, in the case where the video signal line and other wiring line cross each other, it is general that crossing is made at gate electrode wiring lines. In this case, interlayer film capacitance becomes parasitic capacitance.
When the interlayer film is formed of an oxide film with a thickness of 500 nm and the width of the cross wiring line is 5 μm, parasitic capacitance is 0.069 fF/μm2*5 μm*30 μm=10.3 fF. If 8 cross points exist for the video signal line of 300 μm, the parasitic capacitance of 10.3 fF*8=82.8 fF is generated. The inter-wiring capacitance becomes 37.8 fF, and the total capacitance becomes 120.6 fF per 300 μm.
FIG. 11 shows the result of simulation of a delay amount similarly to the clock line. The delay time was 8.25 ns, and the delay was larger than the clock line.
In the case where the delay time is large or wiring capacitance is large, the following become problems for a display device.
(1) A time delay in a clock line causes a shift delay in shift of a shift register by the amount of the delay. Moreover, not only a clock delay but also waveform distortion is generated, which causes inferior operation of the shift register. The distortion in a video signal line causes the same data to be written in plural columns on a picture screen or pixels to be blurred, so that the picture quality is degraded.
(2) When inter-wiring capacitance becomes large, mutual interference between clock lines, and mutual interference between video signal lines are generated, which also causes the deterioration of picture quality.
(3) When the inter-wiring capacitance becomes large, and in the case where the clock line and video signal line are driven from the outside, large driving power of an external driving circuit is required and the consumption of electricity also becomes large.
As the capacitance load becomes large, the external driving circuit becomes large and the cost is increased. When a feedback amplifier such as an operational amplifier is used for the external driving circuit, erroneous operations such as oscillation are induced by the capacitance load, which also causes the deterioration of picture quality.